Повторное использование старого компонента в VHDL

Я новичок в VHDL и слежу за лабораториями, предоставленными xilinx, но я потерялся в определенной части. В одной из лабораторий я сделал 2-битный мультиплексор 2to1. В моей текущей лаборатории я должен использовать два старых мультиплексора для создания мультиплексора 3to1. Это вообще не объясняет, как это сделать, поэтому я наношу удар в темноте по этому вопросу. Я получаю следующие коды ошибок.

[HDL 9-806] Синтаксическая ошибка в конце. [C:/Nexys 4 ›Projects/lab1_5_dataflow/lab1_5_dataflow.srcs/sources_1/new/mux_2bit_3_to

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux_2bit_3_to_1_dataflow is
Port ( u : in STD_LOGIC_VECTOR (1 downto 0);
       v : in STD_LOGIC_VECTOR (1 downto 0);
       w : in STD_LOGIC_VECTOR (1 downto 0);
       s : in STD_LOGIC_VECTOR (1 downto 0);
       o : out STD_LOGIC_VECTOR (1 downto 0));
end mux_2bit_3_to_1_dataflow;

architecture Behavioral of mux_2bit_3_to_1_dataflow is
component mux_2bitentity mux_2bit_2_to_1 is
Port ( x : in STD_LOGIC_VECTOR (1 downto 0);
       y : in STD_LOGIC_VECTOR (1 downto 0);
       s : in STD_LOGIC;
       m : out STD_LOGIC_VECTOR (1 downto 0));
end mux_2bit_2_to_1;

architecture Behavioral of mux_2bit_2_to_1 is

begin
m(0) <= (x(0) and not s) or (y(0) and s);
m(1) <= (x(1) and not s) or (y(1) and s);


end Behavioral;
to_1 port
(
    x, y : in STD_LOGIC_VECTOR;
    s : in STD_LOGIC;
    m : out STD_LOGIC_VECTOR
) end component;
signal a : STD_LOGIC_VECTOR;
begin
mux1 : mux_2bitentity mux_2bit_2_to_1 is
Port ( x : in STD_LOGIC_VECTOR (1 downto 0);
       y : in STD_LOGIC_VECTOR (1 downto 0);
       s : in STD_LOGIC;
       m : out STD_LOGIC_VECTOR (1 downto 0));
end mux_2bit_2_to_1;

architecture Behavioral of mux_2bit_2_to_1 is

begin
m(0) <= (x(0) and not s) or (y(0) and s);
m(1) <= (x(1) and not s) or (y(1) and s);


end Behavioral;
to_1 port map (
    x => u;                                            LINE 52
    y => v;
    s => s(1);
    m => a                                             LINE 55
);

mux2 : mux_2bitentity mux_2bit_2_to_1 is
Port ( x : in STD_LOGIC_VECTOR (1 downto 0);
       y : in STD_LOGIC_VECTOR (1 downto 0);
       s : in STD_LOGIC;
       m : out STD_LOGIC_VECTOR (1 downto 0));
end mux_2bit_2_to_1;

architecture Behavioral of mux_2bit_2_to_1 is

begin
m(0) <= (x(0) and not s) or (y(0) and s);
m(1) <= (x(1) and not s) or (y(1) and s);


end Behavioral;
to_1 port map (
     x => a;                                           LINE 59
     y => w;
     s => s(0);
     m => o;                                           LINE 62
);
    

end Behavioral;

dat›aflow.vhd:48]

[HDL 9-806] Синтаксическая ошибка около ;. [C:/Nexys 4 ›Projects/lab1_5_dataflow/lab1_5_dataflow.srcs/sources_1/new/mux_2bit_3_to

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux_2bit_3_to_1_dataflow is
Port ( u : in STD_LOGIC_VECTOR (1 downto 0);
       v : in STD_LOGIC_VECTOR (1 downto 0);
       w : in STD_LOGIC_VECTOR (1 downto 0);
       s : in STD_LOGIC_VECTOR (1 downto 0);
       o : out STD_LOGIC_VECTOR (1 downto 0));
end mux_2bit_3_to_1_dataflow;

architecture Behavioral of mux_2bit_3_to_1_dataflow is
component mux_2bitentity mux_2bit_2_to_1 is
Port ( x : in STD_LOGIC_VECTOR (1 downto 0);
       y : in STD_LOGIC_VECTOR (1 downto 0);
       s : in STD_LOGIC;
       m : out STD_LOGIC_VECTOR (1 downto 0));
end mux_2bit_2_to_1;

architecture Behavioral of mux_2bit_2_to_1 is

begin
m(0) <= (x(0) and not s) or (y(0) and s);
m(1) <= (x(1) and not s) or (y(1) and s);


end Behavioral;
to_1 port
(
    x, y : in STD_LOGIC_VECTOR;
    s : in STD_LOGIC;
    m : out STD_LOGIC_VECTOR
) end component;
signal a : STD_LOGIC_VECTOR;
begin
mux1 : mux_2bitentity mux_2bit_2_to_1 is
Port ( x : in STD_LOGIC_VECTOR (1 downto 0);
       y : in STD_LOGIC_VECTOR (1 downto 0);
       s : in STD_LOGIC;
       m : out STD_LOGIC_VECTOR (1 downto 0));
end mux_2bit_2_to_1;

architecture Behavioral of mux_2bit_2_to_1 is

begin
m(0) <= (x(0) and not s) or (y(0) and s);
m(1) <= (x(1) and not s) or (y(1) and s);


end Behavioral;
to_1 port map (
    x => u;                                            LINE 52
    y => v;
    s => s(1);
    m => a                                             LINE 55
);

mux2 : mux_2bitentity mux_2bit_2_to_1 is
Port ( x : in STD_LOGIC_VECTOR (1 downto 0);
       y : in STD_LOGIC_VECTOR (1 downto 0);
       s : in STD_LOGIC;
       m : out STD_LOGIC_VECTOR (1 downto 0));
end mux_2bit_2_to_1;

architecture Behavioral of mux_2bit_2_to_1 is

begin
m(0) <= (x(0) and not s) or (y(0) and s);
m(1) <= (x(1) and not s) or (y(1) and s);


end Behavioral;
to_1 port map (
     x => a;                                           LINE 59
     y => w;
     s => s(0);
     m => o;                                           LINE 62
);
    

end Behavioral;

dat›aflow.vhd:52]

[HDL 9-806] Синтаксическая ошибка около =›. [C:/Nexys 4 ›Projects/lab1_5_dataflow/lab1_5_dataflow.srcs/sources_1/new/mux_2bit_3_to

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux_2bit_3_to_1_dataflow is
Port ( u : in STD_LOGIC_VECTOR (1 downto 0);
       v : in STD_LOGIC_VECTOR (1 downto 0);
       w : in STD_LOGIC_VECTOR (1 downto 0);
       s : in STD_LOGIC_VECTOR (1 downto 0);
       o : out STD_LOGIC_VECTOR (1 downto 0));
end mux_2bit_3_to_1_dataflow;

architecture Behavioral of mux_2bit_3_to_1_dataflow is
component mux_2bitentity mux_2bit_2_to_1 is
Port ( x : in STD_LOGIC_VECTOR (1 downto 0);
       y : in STD_LOGIC_VECTOR (1 downto 0);
       s : in STD_LOGIC;
       m : out STD_LOGIC_VECTOR (1 downto 0));
end mux_2bit_2_to_1;

architecture Behavioral of mux_2bit_2_to_1 is

begin
m(0) <= (x(0) and not s) or (y(0) and s);
m(1) <= (x(1) and not s) or (y(1) and s);


end Behavioral;
to_1 port
(
    x, y : in STD_LOGIC_VECTOR;
    s : in STD_LOGIC;
    m : out STD_LOGIC_VECTOR
) end component;
signal a : STD_LOGIC_VECTOR;
begin
mux1 : mux_2bitentity mux_2bit_2_to_1 is
Port ( x : in STD_LOGIC_VECTOR (1 downto 0);
       y : in STD_LOGIC_VECTOR (1 downto 0);
       s : in STD_LOGIC;
       m : out STD_LOGIC_VECTOR (1 downto 0));
end mux_2bit_2_to_1;

architecture Behavioral of mux_2bit_2_to_1 is

begin
m(0) <= (x(0) and not s) or (y(0) and s);
m(1) <= (x(1) and not s) or (y(1) and s);


end Behavioral;
to_1 port map (
    x => u;                                            LINE 52
    y => v;
    s => s(1);
    m => a                                             LINE 55
);

mux2 : mux_2bitentity mux_2bit_2_to_1 is
Port ( x : in STD_LOGIC_VECTOR (1 downto 0);
       y : in STD_LOGIC_VECTOR (1 downto 0);
       s : in STD_LOGIC;
       m : out STD_LOGIC_VECTOR (1 downto 0));
end mux_2bit_2_to_1;

architecture Behavioral of mux_2bit_2_to_1 is

begin
m(0) <= (x(0) and not s) or (y(0) and s);
m(1) <= (x(1) and not s) or (y(1) and s);


end Behavioral;
to_1 port map (
     x => a;                                           LINE 59
     y => w;
     s => s(0);
     m => o;                                           LINE 62
);
    

end Behavioral;

dat›aflow.vhd:55]

[HDL 9-806] Синтаксическая ошибка около ;. [C:/Nexys 4 ›Projects/lab1_5_dataflow/lab1_5_dataflow.srcs/sources_1/new/mux_2bit_3_to

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux_2bit_3_to_1_dataflow is
Port ( u : in STD_LOGIC_VECTOR (1 downto 0);
       v : in STD_LOGIC_VECTOR (1 downto 0);
       w : in STD_LOGIC_VECTOR (1 downto 0);
       s : in STD_LOGIC_VECTOR (1 downto 0);
       o : out STD_LOGIC_VECTOR (1 downto 0));
end mux_2bit_3_to_1_dataflow;

architecture Behavioral of mux_2bit_3_to_1_dataflow is
component mux_2bitentity mux_2bit_2_to_1 is
Port ( x : in STD_LOGIC_VECTOR (1 downto 0);
       y : in STD_LOGIC_VECTOR (1 downto 0);
       s : in STD_LOGIC;
       m : out STD_LOGIC_VECTOR (1 downto 0));
end mux_2bit_2_to_1;

architecture Behavioral of mux_2bit_2_to_1 is

begin
m(0) <= (x(0) and not s) or (y(0) and s);
m(1) <= (x(1) and not s) or (y(1) and s);


end Behavioral;
to_1 port
(
    x, y : in STD_LOGIC_VECTOR;
    s : in STD_LOGIC;
    m : out STD_LOGIC_VECTOR
) end component;
signal a : STD_LOGIC_VECTOR;
begin
mux1 : mux_2bitentity mux_2bit_2_to_1 is
Port ( x : in STD_LOGIC_VECTOR (1 downto 0);
       y : in STD_LOGIC_VECTOR (1 downto 0);
       s : in STD_LOGIC;
       m : out STD_LOGIC_VECTOR (1 downto 0));
end mux_2bit_2_to_1;

architecture Behavioral of mux_2bit_2_to_1 is

begin
m(0) <= (x(0) and not s) or (y(0) and s);
m(1) <= (x(1) and not s) or (y(1) and s);


end Behavioral;
to_1 port map (
    x => u;                                            LINE 52
    y => v;
    s => s(1);
    m => a                                             LINE 55
);

mux2 : mux_2bitentity mux_2bit_2_to_1 is
Port ( x : in STD_LOGIC_VECTOR (1 downto 0);
       y : in STD_LOGIC_VECTOR (1 downto 0);
       s : in STD_LOGIC;
       m : out STD_LOGIC_VECTOR (1 downto 0));
end mux_2bit_2_to_1;

architecture Behavioral of mux_2bit_2_to_1 is

begin
m(0) <= (x(0) and not s) or (y(0) and s);
m(1) <= (x(1) and not s) or (y(1) and s);


end Behavioral;
to_1 port map (
     x => a;                                           LINE 59
     y => w;
     s => s(0);
     m => o;                                           LINE 62
);
    

end Behavioral;

dat›aflow.vhd:59]

[HDL 9-806] Синтаксическая ошибка около =›. [C:/Nexys 4 ›Projects/lab1_5_dataflow/lab1_5_dataflow.srcs/sources_1/new/mux_2bit_3_to

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux_2bit_3_to_1_dataflow is
Port ( u : in STD_LOGIC_VECTOR (1 downto 0);
       v : in STD_LOGIC_VECTOR (1 downto 0);
       w : in STD_LOGIC_VECTOR (1 downto 0);
       s : in STD_LOGIC_VECTOR (1 downto 0);
       o : out STD_LOGIC_VECTOR (1 downto 0));
end mux_2bit_3_to_1_dataflow;

architecture Behavioral of mux_2bit_3_to_1_dataflow is
component mux_2bitentity mux_2bit_2_to_1 is
Port ( x : in STD_LOGIC_VECTOR (1 downto 0);
       y : in STD_LOGIC_VECTOR (1 downto 0);
       s : in STD_LOGIC;
       m : out STD_LOGIC_VECTOR (1 downto 0));
end mux_2bit_2_to_1;

architecture Behavioral of mux_2bit_2_to_1 is

begin
m(0) <= (x(0) and not s) or (y(0) and s);
m(1) <= (x(1) and not s) or (y(1) and s);


end Behavioral;
to_1 port
(
    x, y : in STD_LOGIC_VECTOR;
    s : in STD_LOGIC;
    m : out STD_LOGIC_VECTOR
) end component;
signal a : STD_LOGIC_VECTOR;
begin
mux1 : mux_2bitentity mux_2bit_2_to_1 is
Port ( x : in STD_LOGIC_VECTOR (1 downto 0);
       y : in STD_LOGIC_VECTOR (1 downto 0);
       s : in STD_LOGIC;
       m : out STD_LOGIC_VECTOR (1 downto 0));
end mux_2bit_2_to_1;

architecture Behavioral of mux_2bit_2_to_1 is

begin
m(0) <= (x(0) and not s) or (y(0) and s);
m(1) <= (x(1) and not s) or (y(1) and s);


end Behavioral;
to_1 port map (
    x => u;                                            LINE 52
    y => v;
    s => s(1);
    m => a                                             LINE 55
);

mux2 : mux_2bitentity mux_2bit_2_to_1 is
Port ( x : in STD_LOGIC_VECTOR (1 downto 0);
       y : in STD_LOGIC_VECTOR (1 downto 0);
       s : in STD_LOGIC;
       m : out STD_LOGIC_VECTOR (1 downto 0));
end mux_2bit_2_to_1;

architecture Behavioral of mux_2bit_2_to_1 is

begin
m(0) <= (x(0) and not s) or (y(0) and s);
m(1) <= (x(1) and not s) or (y(1) and s);


end Behavioral;
to_1 port map (
     x => a;                                           LINE 59
     y => w;
     s => s(0);
     m => o;                                           LINE 62
);
    

end Behavioral;

dat›aflow.vhd:62]

Вот мой код для основного исходного файла.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux_2bit_3_to_1_dataflow is
Port ( u : in STD_LOGIC_VECTOR (1 downto 0);
       v : in STD_LOGIC_VECTOR (1 downto 0);
       w : in STD_LOGIC_VECTOR (1 downto 0);
       s : in STD_LOGIC_VECTOR (1 downto 0);
       o : out STD_LOGIC_VECTOR (1 downto 0));
end mux_2bit_3_to_1_dataflow;

architecture Behavioral of mux_2bit_3_to_1_dataflow is
component mux_2bitentity mux_2bit_2_to_1 is
Port ( x : in STD_LOGIC_VECTOR (1 downto 0);
       y : in STD_LOGIC_VECTOR (1 downto 0);
       s : in STD_LOGIC;
       m : out STD_LOGIC_VECTOR (1 downto 0));
end mux_2bit_2_to_1;

architecture Behavioral of mux_2bit_2_to_1 is

begin
m(0) <= (x(0) and not s) or (y(0) and s);
m(1) <= (x(1) and not s) or (y(1) and s);


end Behavioral;
to_1 port
(
    x, y : in STD_LOGIC_VECTOR;
    s : in STD_LOGIC;
    m : out STD_LOGIC_VECTOR
) end component;
signal a : STD_LOGIC_VECTOR;
begin
mux1 : mux_2bitentity mux_2bit_2_to_1 is
Port ( x : in STD_LOGIC_VECTOR (1 downto 0);
       y : in STD_LOGIC_VECTOR (1 downto 0);
       s : in STD_LOGIC;
       m : out STD_LOGIC_VECTOR (1 downto 0));
end mux_2bit_2_to_1;

architecture Behavioral of mux_2bit_2_to_1 is

begin
m(0) <= (x(0) and not s) or (y(0) and s);
m(1) <= (x(1) and not s) or (y(1) and s);


end Behavioral;
to_1 port map (
    x => u;                                            LINE 52
    y => v;
    s => s(1);
    m => a                                             LINE 55
);

mux2 : mux_2bitentity mux_2bit_2_to_1 is
Port ( x : in STD_LOGIC_VECTOR (1 downto 0);
       y : in STD_LOGIC_VECTOR (1 downto 0);
       s : in STD_LOGIC;
       m : out STD_LOGIC_VECTOR (1 downto 0));
end mux_2bit_2_to_1;

architecture Behavioral of mux_2bit_2_to_1 is

begin
m(0) <= (x(0) and not s) or (y(0) and s);
m(1) <= (x(1) and not s) or (y(1) and s);


end Behavioral;
to_1 port map (
     x => a;                                           LINE 59
     y => w;
     s => s(0);
     m => o;                                           LINE 62
);
    

end Behavioral;

А вот исходный файл мультиплексора 2 к 1, который я добавил в проект.

entity mux_2bit_2_to_1 is
Port ( x : in STD_LOGIC_VECTOR (1 downto 0);
       y : in STD_LOGIC_VECTOR (1 downto 0);
       s : in STD_LOGIC;
       m : out STD_LOGIC_VECTOR (1 downto 0));
end mux_2bit_2_to_1;

architecture Behavioral of mux_2bit_2_to_1 is

begin
m(0) <= (x(0) and not s) or (y(0) and s);
m(1) <= (x(1) and not s) or (y(1) and s);


end Behavioral;

vivado vhdl

Peter Nguyen 02.07.2015 источник

Ответы (1)

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1
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Две вещи. Во-первых, вы пропускаете точку с запятой перед end component;:

component mux_2bit_2_to_1
port (
    x, y : in STD_LOGIC_VECTOR;
    s : in STD_LOGIC;
    m : out STD_LOGIC_VECTOR
); -- <--- semicolon here
end component;

Во-вторых, вы используете двоеточие при назначении портов в экземпляре:

mux1 : mux_2bit_2_to_1 port map (
    x => u,
    y => v,
    s => s(1),
    m => a
);

Наконец, во втором экземпляре вы используете точку с запятой для последнего порта (m). Во-первых, нет точки с запятой при создании экземпляра порта и, во-вторых, нет двоеточия в последнем назначении перед закрывающими скобками.

Jonathan Drolet 02.07.2015

Повторное использование старого компонента в VHDL

Ответы (1)

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